| Summary: Due to short time to market and reuse of designs, System on Chip (SoC) architectures that are composed of commercially of-the-shelf available intellectual property (IP) blocks are becoming popular. There is a trend to develop (reconfigurable) SoC architectures that are flexible enough to run a range of applications within a certain domain. Common practice is to map applications to SoC architectures at design-time. An application is modeled as a set of communicating processes. For a number of reasons (e.g. dynamic resource management, adaptation to required resources and yield improvement) it is preferred to perform the mapping at run-time. The main research question is to provide the theoretical framework for efficient and flexible mapping/optimization algorithms that can be used at run-time. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required Quality of Service. Utilisation: The theoretical results of this research can be applied almost immediately within other running projects of the participating chairs, such as 4S and AAF. The 4S project and AAF project are working on similar issues, but their focus is at the design of the underlying SoC architecture and applications whereas the focus in this proposal is on the theoretical issues related to run-time resource allocation. In the above mentioned projects we have a tight collaboration with industrial partners, such as Philips Research and Atmel. In recent meetings with these companies, we discovered that they both are highly interested in application of these research results. However, before the results can be applied in an industrial setting a number of tough (theoretical) problems have to be solved. |
